Referring now to FIGS. 1 and 2, an incoming bitstream 10 includes synchronization (sync) marks 12 that are positioned after a sync field 14 to identify a starting bit of user data 16. Typically, the sync field 14 includes a repeating pattern such as “1100”. A conventional sync mark detector 30 is connected to a front end 32 of a communications channel such as a wireless link, a disk drive or any other communications channel. The front end 32 provides the incoming bitstream 10 to a bit decision circuit 33 such as a Viterbi circuit. An output of the bit decision circuit 33 is coupled to a buffer 34 such as a first in first out (FIFO) buffer. A comparison circuit 36 of the sync mark detector 30 declares synchronization (or a sync mark found state) if bits stored in the buffer 34 match a predefined sync mark 38 according to a predetermined rule 40. For example for a 3 byte sync mark, the sync mark found state can be declared if 1 of 3 bytes are detected. For a 4 byte sync mark, the sync mark found state can be declared if 2 out of 4 bytes are detected.
Referring now to FIG. 1, three different types of sync mark errors may occur during the synchronization process. A sync mark miss is declared if the sync mark detector 30 does not find the predefined sync mark 38 in the incoming bitstream 10. In this case, a retry is required. Misalignment errors occur if the sync mark detector 30 declares the sync mark found state at a wrong position in the incoming bitstream 10. In particular, early alignment 42 refers to the declaration of the sync mark found state before the correct position in the incoming bitstream 10. Late alignment 46 refers to the declaration of the sync mark found state after the correct sync mark position in the incoming bitstream 10. For example when early or late alignment 42 or 46 occur in a disk drive, the bit decision circuit 33 continues operating for the remainder of a current sector and causes an error correction coding (ECC) failure. In this situation, a retry request is generated at the end of the sector.
Late alignment 46 occurs when a sync mark miss happens. Bits of the user data 16 after the sync mark 12 match the last several bits of the sync mark 38 so that a sync mark found is declared after the correct position in the incoming bitstream 10. In this situation, the probability of the late alignment 46 is less than the probability of the sync mark miss. Early alignment 42 happens when the end of the sync field 14 combined with the beginning of the sync mark 12 is similar to the sync mark 38.
Referring now to FIG. 3, an example of early alignment is shown. The sync mark includes two 5 bit symbols (11000 and 00011) and a 1-out-of-2 symbol matching rule is used. A single error event, identified by “−” causes the first 5 bits to be the same as the first sync mark symbol and leads to early alignment 42.